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 "cells": [
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   "cell_type": "markdown",
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   "source": [
    "#   [Py4Hw User Guide](../UserGuide.ipynb)> 7.1 RTL Generation"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "py4hw generates Verilog RTL Code.\n",
    "\n",
    "As many high level language RTL generation tool, it (still) creates HDL code which is ugly to the eyes of a typical Hardware designer.\n",
    "\n",
    "The reason for this is explained in [section 8.1](../s08/Structures.ipynb), but we are working to improve significantly this issue compared with other similar frameworks.\n",
    "\n",
    "\n"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 1,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "// This file was automatically created by py4hw RTL generator\n",
      "module Circuit (\n",
      "\tinput  a,\n",
      "\tinput  b,\n",
      "\toutput  r,\n",
      "\toutput  c);\n",
      "\n",
      "assign r = a | b;\n",
      "assign c = a ^ b;\n",
      "endmodule\n",
      "\n"
     ]
    }
   ],
   "source": [
    "import py4hw\n",
    "\n",
    "class Circuit(py4hw.Logic):\n",
    "    \n",
    "    def __init__(self, parent, name, a, b, r, c):\n",
    "        super().__init__(parent, name)\n",
    "        \n",
    "        a = self.addIn('a', a)\n",
    "        b = self.addIn('b', b)\n",
    "        r = self.addOut('r', r)\n",
    "        c = self.addOut('c', c)\n",
    "\n",
    "        py4hw.Or2(self, 'or', a,b,r)\n",
    "        py4hw.Xor2(self, 'xor', a,b,c)\n",
    "        \n",
    "        \n",
    "sys = py4hw.HWSystem()\n",
    "a = sys.wire('a', 1)\n",
    "b = sys.wire('b', 1)\n",
    "c = sys.wire('c', 1)\n",
    "r = sys.wire('r', 1)\n",
    "\n",
    "ha = Circuit(sys, 'half_adder', a, b, r, c)\n",
    "\n",
    "rtlgen = py4hw.VerilogGenerator(ha)\n",
    "\n",
    "print(rtlgen.getVerilog(noInstanceNumber=True))"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "py4hw uses different techniques to generate the Verilog for different type of circuits.\n",
    "In some simple primitive circuits (like and, or, etc) py4hw uses inlining to automatically embed assign expressions in the output Verilog code.\n",
    "\n"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": null,
   "metadata": {},
   "outputs": [],
   "source": []
  }
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